1. Field of the Invention
The present invention relates to an electrically readable and writable non-volatile semiconductor storage device and a method of writing data thereto.
2. Description of the Related Art
Non-volatile OTP (One-Time Programmable) memory has been an essential element in semiconductor integrated circuits where the stored data is not lost even when the power is turned off. The OTP memory has been widely used for adding redundancy in mass storage memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory); for tuning of analog circuits: for storing codes such as encryption keys: for storing chip IDs such as history and management information in manufacturing process; and the like.
For memory redundancy applications, laser-fuse ROM (Read Only Memory) with laser fuses has been used as a cheapest non-volatile memory where information is stored in an irreversible manner through laser beam blowing of the fuses. The laser fuse ROM requires a specially-designed fuse-blow machine and the associated blowing process, which involves necessary test costs. In addition, since the minimum dimension of a laser fuse ROM is determined by the wavelength of the laser beam in use, the laser fuse ROM does not keep in step with refinement of other circuit parts, causing a gradual increase in the percentage of its occupation area. Further, the laser fuse ROM can be programmed only at wafer level due to its programming method, and hence cannot be used for recovery from failure in high-speed test after packaging, Built-in Self Repair (BISR) by a test circuit mounted in the chip, and so on.
In addition, there are demands in systems with laser fuse ROM for mounting a electrically-programmable non-volatile memory. In this case, systems including multiple chips may store various types of information in independent EEPROMs (Electrically Erasable Programmable Read Only Memory) chip. However, the SoC (System on Chip) where systems are integrated on one chip must also have a non-volatile memory therein. Consolidation of non-volatile memory that stores charges in a floating gate would require additional masks and associated processes, causing an increase in cost. Information such as memory redundancy information that is stored in a non-volatile memory needs not necessarily be rewritten many times. Therefore, there are great demands for OTP memory, because it can be formed by currently-available standard CMOS process.
Those storage elements used in the OTP memory that store information by changing their element characteristics in an irreversible manner are collectively referred to hereinafter as “fuse elements”. In addition, among these, those elements are collectively referred to as “eFuses (Electrical Fuses)” that electrically change their element characteristics in an irreversible manner. One of the eFuses that can be used in standard CMOS process includes a “Gate-Ox eFuse” that utilizes the decrease in resistance by formation of a conduction spot due to dielectric breakdown caused by applying high voltage to a gate insulation film of a MOSFET. Those fuse elements are referred to as “antifuses” that become high-resistance state during non-programmed state and low-resistance state after being programmed. It is herein defined that “0” data is stored in an antifuse in high-resistance state before programming, while “1” data being stored in low-resistance state after programming, respectively. An example of conventional OTP memory with such antifuses is disclosed in Non-Patent Document 1 (A 65 nm Pure CMOS One-time Programmable Memory Using a Two-Port Antifuse Cell Implemented in a Matrix Structure”, pp. 211-215, IEEE Asian Solid-State Circuits Conference 2007). In Non-Patent Document 1, a gate insulation film of a p-type MOSFET is used as an antifuse and a high-voltage power supply circuit for programming is arranged external to a memory array.
However, the above-mentioned antifuse suffers from a larger high-voltage stress on each memory cell if there is any leakage in a memory cell (decrease in voltage of a node) or the fluctuation of the supply voltage. This leakage is caused by: high-temperature condition; and decrease in threshold voltage due to the manufacturing variation. In addition, the total amount of time for writing increases due to an increase in number of bits to be written at one time, the stress application time also increases for non-selected cells. This situation where both the strength and application time of such high voltage stress increases may degrade the gate insulation film of the non-selected cell, to which “1” data could be incorrectly written accordingly. Although some memory cells can pass the final test before shipment depending upon the degree of degradation, they may fail during actual use due to the secular change, posing a serious problem concerning the reliability.